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Power Supply IC Series for TFT-LCD Panels
Single-channel Source Voltage Output Power Supply + Gamma Buffer Amp ICs
BD8151EFV,BD8157EFV
No.09035EBT11
Description The BD8151EFV,BD8157EFV power supply IC are designed for use with TFT-LCD panels. It incorporates a built-in source voltage step-up switching regulator and gamma correction buffer amp. The combination of a source power supply and gamma correction buffer on a single chip delivers significant cost savings. Compatible with input voltages from 2.5 V to 5.5 V (BD8151EFV), 2.1 V to 4.0 V (BD8157EFV), the IC supports low-voltage operation and reaches over 85% efficiency with a 2.5 V input, contributing to low power consumption designs. Features 1) Single-chip implementation of a source power supply and gamma correction buffer 2) Support for low-voltage operation, with input voltages from 2.5 V to 5.5 V (BD8151EFV) 2.1 V to 4.0 V (BD8157EFV) 3) Built-in 1.4 A, 0.2 low-voltage FET 4) Switchable step-up DC/DC switching frequencies: 600 kHz/1.2 MHz 5) Current mode PWM control 6) Under-voltage lockout protection circuit 7) Built-in overcurrent protection circuit 8) Built-in thermal shutdown circuit Applications Satellite navigation systems, laptop PC TFT LCD panels LCD monitor panels Absolute maximum ratings (Ta = 25) Parameter Power supply voltage Power dissipation Operating temperature range Storage temperature range Switching pin current Switching pin voltage VS voltage Maximum junction temperature BD8151EFV BD8157EFV
Symbol Vcc Pd Topr Tstg Isw Vsw VS Tjmax
Limit 7 1000* -40 to +85 -40 to +125 -55 to +150 1.5** 15 15 150
Unit V mW A V V C
* Reduced by 8 mW/ over 25, when mounted on a glass epoxy board (70 mm x 70 mm x 1.6 mm). ** Must not exceed Pd.
Recommended Operating Ranges (Ta = 25) Parameter Power supply voltage BD8151EFV Power supply voltage BD8157EFV Switching current Switching pin voltage VS pin voltage Symbol Vcc Vcc ISW VSW VS Limit Min. 2.5 2.1 -- -- 5 Typ. 3.3 2.5 -- -- 9 Max. 5.5 4.0 1.4 14 14 Unit V V A V V
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1/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Technical Note
Electrical Characteristics BD8151EFV (Unless otherwise specified, Ta = 25; Vcc = 3.3V, ENB = 3.3V) Limit Parameter Symbol Unit Conditions Min. Typ. Max. [Triangular waveform oscillator] Oscillating frequency 1 Oscillating frequency 2 [Overcurrent protection circuit] Overcurrent limit [Soft start circuit] SS source current Off threshold voltage On threshold voltage [Error amp] Input bias current Feedback voltage [Output] On resistance Max. duty ratio [ENB] ENB on voltage ENB off voltage [Overall] Standby current Average consumption current [Amp] Input bias current Drive current 1 Drive current 2 Max. output current Min. output current Ibo IOO1 IOO2 Voho Vohl -1 50 150 VS-0.16 -- 0 70 200 VS-0.1 0.1 1 140 400 -- 0.16 A mA mA V V IN += 4.5 V OUT1 to OUT4 VCOM Io = -5 mA, IN += VS Io = 5 mA, IN += 0 V ISTB ICC -- -- 0 1.2 10 2.4 A mA VENB = 0 V no switching VON VOFF Vcc x 0.7 -- Vcc 0 -- Vcc x 0.3 V V RON DMAX -- 72 200 80 300 88 m % *Isw = 1 A RL = 100 IB VFB -- 1.232 0.1 1.245 0.5 1.258 A V Buffer ISO VUTOFF VUTON 6 2.1 2.0 10 2.2 2.1 14 2.3 2.2 A V V Vss = 0.5 V [Under-voltage lockout protection circuit] ISW -- 2 -- A FOSC1 FOSC2 540 1.08 600 1.20 660 1.32 kHz MHz FCLK = 0 V FCLK = Vcc
This product is not designed for protection against radio active rays. * Design guarantee (No total shipment inspection is made.)
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2/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Technical Note
Electrical Characteristics BD8157EFV (Unless otherwise specified, Ta = 25; Vcc = 2.5V, ENB = 2.5V) Limit Parameter Symbol Unit Conditions Min. Typ. Max. [Triangular waveform oscillator] Oscillating frequency 1 Oscillating frequency 2 [Overcurrent protection circuit] Overcurrent limit [Soft start circuit] SS source current Off threshold voltage On threshold voltage [Error amp] Input bias current Feedback voltage [Output] On resistance Max. duty ratio [ENB] ENB on voltage ENB off voltage [Overall] Standby current Average consumption current [Amp] Input bias current Drive current 1 Drive current 2 Max. output current Min. output current Ibo IOO1 IOO2 Voho Vohl -1 50 120 VS-0.16 -- 0 70 200 VS-0.1 0.1 1 140 400 -- 0.16 A mA mA V V IN += 4.5 V OUT1 to OUT4 VCOM Io = -5 mA, IN += VS Io = 5 mA, IN += 0 V ISTB ICC -- -- 0 1.2 10 2.4 A mA VENB = 0 V no switching VON VOFF Vcc x 0.7 -- Vcc 0 -- Vcc x 0.3 V V RON DMAX -- 75 200 85 600 95 m % *Isw = 1 A RL = 100 IB VFB -- 1.232 0.1 1.245 0.5 1.258 A V Buffer ISO VUTOFF VUTON 6 1.7 1.6 10 1.8 1.7 14 1.9 1.8 A V V Vss = 0.5 V [Under-voltage lockout protection circuit] ISW -- 2 -- A FOSC1 FOSC2 480 0.96 600 1.20 720 1.44 kHz MHz FCLK = 0 V FCLK = Vcc
This product is not designed for protection against radio active rays. * Design guarantee (No total shipment inspection is made.)
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3/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Reference Data (Unless otherwise specified, Ta = 25)
1.75 STANDBY CURRENT : ICC[A] . SUPPLY CURRENT: ICC[mA] . 1.50 1.25 1.00 2.0
REFERENCE VOLTAGE : VREF[V] .
Technical Note
1.260 1.255 1.250 1.245 1.240 1.235 1.230
0 1 2 3 4
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0
-40
125
25
0.75 0.50 0.25 0.00
25
-40
150
0 0.5 1
2
3
4
5
6
-40
-15
10
35
60
85
110
SUPPLY VOLTAGE : VCC[V]
SUPPLY VOLTAGE : VCC[V]
AMBIENT TEMPERATURE : Ta[]
Fig. 1 Total Supply Current
Fig. 2 Standby Current
Fig. 3 Reference Voltage Temperature
2000
0
REFERENCE VOLTAGE : VREF[V]
2.0
BD8157EFV
1.5
SS CURRENT : ISS[A]
-4
SWITCHING FREQUENCY : FSW[kHz]
1500
VFCLK=VCC
-8
1.0
1000
VFCLK=GND
-12
0.5
500
-16
-20 0 0.5 1 1.5 2
2 .4
0.0 0 1.5 3 4.5 6 7.5
0 -40
-15
10
35
60
85
110
SS VOLTAGE : VSS[V]
SUPPLY VOLTAGE : VCC[V]
AMBIENT TEMPERATURE : Ta[]
Fig. 4 SS Source Current
20 FCLK CURRENT : FCLK[A] .
ENB CURRENT : ENB[A] . 20
Fig. 5 Reference Voltage Temperature
100 COMP CURRENT : ICOMP[uA] .
Fig. 6 Switching Frequency Temperature
15
125
15
50
125
10
10
25
25
0
5
-40
5
-40
-50
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
-100 1.0
1.1
1.2
1.3
1.4
1.5
FCLK VOLTAGE : FCLK[V]
ENB VOLTAGE : VENB[V]
COMP VOLTAGE : VCOMP[V]
Fig. 7 FCLK Pin Current
100
Fig. 8 ENB Pin Current
100 VCC=2.5V f=600kHz
Fig. 9 COMP Sinking vs Source Current
100
VCC=3.3V f=600kHz
90 EFFICIENCY [%]
95
90 EFFICIENCY [%]
Max Duty [%]
80
VCC=2.5V f=1200kHz
80
90
70
70
VCC=3.3V f=1200kHz
85
60
60
BD8157EFV
80 -40
BD8151EFV
50
50
0 40 80 120 125
0
0.05
0.1
0.15
0.2
0.25
0.3
0 0.02
0.15
0.3
0.45
0.6
AMBIENT TEMPERATURE : Ta[]
OUTPUT CURRENT : IO[A]
OUTPUT CURRENT : IO[A]
Fig. 10 Max. Duty Ratio Temperature
Fig. 11 Vcc = 2.5 V Power Efficiency
Fig. 12 Vcc = 3.3 V Power Efficiency
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4/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Reference Data (Unless otherwise specified, Ta = 25)
100
Technical Note
0.8 MAXIMUM CURRENT : IOMAX[A] .
BD8157EFV
0.6
90 EFFICIENCY [%]
Io=0mA F=600kHz
Io=100mA
80
0.4
70
VO F=1200kHz
60
0.2
100mV/div
BD8157EFV
50 2.0 2.5 3.0 3.5 4.0
20us/div
0 2.1
2.4
2.7
3.0
3.3
3.6
3.9
SUPPLY VOLTAGE : VCC[V]
SUPPLY VOLTAGE : VCC[V]
Fig. 13 Power Efficiency vs Power Supply Voltage
10
10
Fig. 14 Max. Load Current vs Power Supply Voltage
9
Fig. 15 Load Response Waveform
OUTPUT VOLTAGE : VO[V]
8
8.8
1
VS CURRENT : IS[mA]
DELAY TIME [ms]
6
8.6
4
8.4
0.1
2
8.2
0.01 0.001
0
0.01 SS CAPACITANCE [F]
0.1
0
5
10
15
8 0.0
0.1 LOAD CURRENT : IO[A]
1.0
VS VOLTAGE : VS[V]
Fig. 16 SS Capacitance vs Delay Time
10 OFFSET VOLTAGE:VOFFSET[mV
Fig. 17 VS Pin Current
Fig. 18 Output voltage Load Regulation 1
9 8 OUTPUT VOLTAGE : VOUT[V]
9 8 OUTPUT VOLTAGE : VOUT[V]
5 0 -5 -10 -15 -20 1 2 3 4 5 6 7 8 9 BUFFER INPUT VOLTAGE:VIN[V]
7 6 5 4 3 2 1 0 0 25 50 75 100 125 150 175 200 OUTPUT CURRENT : IOUT[mA] .
25 125 -40
7 6 5 4 3 2 1 0 -200 -175 -150 -125 -100 -75 -50 -25 OUTPUT CURRENT : IOUT[mA] . 0
-40
25
125
Fig. 19 Buffer Voltage
9 OUTPUT VOLTAGE : VOUT[V] . OUTPUT VOLTAGE : VOUT[V] . 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 300 OUTPUT CURRENT : IOUT[mA] . 9 8 7 6 5 4 3 2 1 0 -300
Fig. 20 Buffer Sinking Current
Fig. 21 Buffer Source Current
-40
25
125
IN
125
25
-40
OUT 1us/div 2V/div
-250 -200 -150 -100 -50 0
OUTPUT CURRENT : IOUT[mA]
Fig. 22 VCOM Sinking Current
Fig. 23 VCOM Source Current
Fig. 24 Slew Rate Waveform
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5/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Pin Assignment Diagram Block Diagram
Technical Note
SW
1
CURRENT SENSE
20
PGND
VCC
2 SLOPE
19 DRV
GND
+ SET
SW VCC ENB FCLK VS COMIN IN1 IN2 IN3 IN4
PGND GND FB COMP SS VCOM OUT1 OUT2 OUT3 OUT4
ENB
3
OSC
LOGIC
RESET SDWN OCP
18 ERR + 1.245V 17
FB
FCLK
4 UVLO TSD PWM +SOFT START
COMP
VS
5
BUFFER SUPPLY
16
SS
COMIN 6
15 VCOM
IN1
7
14
OUT1
IN2
8
13
OUT2
IN3
9
12
OUT3
IN4
10 TOP VIEW
11
OUT4
Fig. 25 Pin Assignment Diagram and Block Diagram Pin Assignment Diagram and Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin name SW VCC ENB FCLK VS COMIN IN1 IN2 IN3 IN4 OUT4 OUT3 OUT2 OUT1 VCOM SS COMP FB GND PGND N-channel power FET drain output Power supply input pin Control input pin Frequency switching pin Buffer power supply input pin VCOM input pin Amp input pin 1 Amp input pin 2 Amp input pin 3 Amp input pin 4 Amp output pin 4 Amp output pin 3 Amp output pin 2 Amp output pin 1 VCOM output pin Soft start current output pin Error amp output pin Error amp inversion input pins Ground pin Ground pin Function
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6/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Description of Operation of Each Block
10uH RB161M-20 10uF
Technical Note
Vo
1 SW
CURRENT SENSE
20 PGND 19 GND DRV SET
VCC 2.5V
10uF
2 VCC 3 ENB 4 FCLK 5 VS UVLO TSD SLOPE
+
100k 15k
OSC
LOGIC
RESET SDWN OCP
18 ERR + 1.245V FB
PWM +SOFT START
17 COMP 16 SS
5.1k 3300pF 0.01uF VCOM
BUFFER SUPPLY
20k 20k
6 COMIN
15 VCOM
20k
20k 20k 20k
7 IN1 8 IN2 9 IN3 10 IN4 TOP VIEW
14 OUT1 13 OUT2 12 OUT3 11 OUT4
V1 V2 V3 V4
20k
Fig. 26 Application Circuit Diagram Error amp (ERR) This is the circuit to compare the reference voltage 1.245 V (Typ.) and the feedback voltage of output voltage. The COM pin voltage resulting from this comparison determines the switching duty. At the time of start, since the soft start is operated by the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage. Oscillator (OSC) This block generates the oscillating frequency. Either a 600 kHz or 1.2 MHz (Typ.) frequency can be selected with the FCLK pin. SLOPE This block generates the triangular waveform from the clock generated by OSC. Generated triangular waveform is sent to the PWM comparator. PWM The COMP pin voltage output by the error amp is compared to the SLOPE block's triangular waveform to determine the switching duty. Since the switching duty is limited by the maximum duty ratio which is decided internally, it does not become 100%. Reference voltage (VREF) This block generates the internal reference voltage of 1.245 V (Typ.). Protection circuit (UVLO/TSD) UVLO (under-voltage lockout protection circuit) shuts down the circuits when the voltages are 2.2 V (Typ.BD8151EFV) 1.8 V (Typ.ND8157EFV) or lower. Thermal shutdown circuit shuts down IC at 175C (Typ.) and recovers at 160C (Typ.). Overcurrent protection circuit (OCP) Current flowing to the power FET is detected by voltage at the CURRENT SENSE and the overcurrent protection operates at 3 A (Typ.). When the overcurrent protection operates, switching is turned off and the SS pin capacity is discharged. Soft start circuit Since the output voltage rises gradually while restricting the current at the time of startup, it is possible to prevent the output voltage overshoot or the inrush current. Buffer amp and VCOM This buffer amp is used to set the gamma correction voltage, which can be set in from 0.2 V to (VOUT - 0.2 V). Use the VOUT resistance division to set the gamma correction voltage. The VCOM voltage is set similarly.
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7/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Timing Chart Startup sequence
Technical Note
VCC
ENB
SS
SW
VO
Fig. 27 Startup sequence Overcurrent protection operating
2.5V
VCC,ENB
SS
SW
VO
IO
Fig. 28 Overcurrent protection operating
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8/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Technical Note
Selecting Application Components (1) Setting the output L constant The coil L to use for output is decided by the rating current ILR and input current maximum value IINMAX of the coil. IINMAX+ IL should not reach the rating value level L
INMAX
Vcc IL Vo
IL
average Co
I current
t Fig. 29 Coil Current Waveform Fig. 30 Output Application Circuit Diagram
Adjust so that IINMAX + IL does not reach the rating current value ILR. At this time, IL can be obtained by the following equation. 1 Vo-Vcc 1 Vcc [A] Where, f is the switching frequency. IL = L Vcc f Set with sufficient margin because the coil L value may have the dispersion of approx. 30%. If the coil current exceeds the rating current ILR of the coil, it may damage the IC internal element. BD8157EFV uses the current mode DC/DC converter control and has the optimized design at the coil value. The following coil values are recommended from the aspects of power efficiency, response and safety. When the coil out of this range is selected, the stable continual operation is not guaranteed such as the switching waveform becomes irregular. Please pay attention to it. Switching frequency: L = 10 H to 22 H at 600 kHz Switching frequency: L = 4.7 H to 15 H at 1,200 kHz (2) Setting the output capacitor For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP allowance value and the drop voltage allowance value at the time of sudden load change. Output ripple voltage is decided by the following equation. 1 Vcc IL (ILMAX) [V] Where, f is the switching frequency. VPP = ILMAXxRESR + fCo Vo 2 Perform setting so that the voltage is within the allowable ripple voltage range. For the drop voltage during sudden load change; VDR, please perform the rough calculation by the following equation. VDR = I Co 10 sec [V]
However, 10 s is the rough calculation value of the DC/DC response speed. Please set the capacitance considering the sufficient margin so that these two values are within the standard value range. (3) Selecting the input capacitor Since the peak current flows between the input and output at the DC/DC converter, a capacitor is required to install at the input side. For this reason, the low ESR capacitor is recommended as an input capacitor which has the value more than 10 F and less than 100 m. If a capacitor out of this range is selected, the excessive ripple voltage is superposed on the input voltage, accordingly it may cause the malfunction of IC. However these conditions may vary according to the load current, input voltage, output voltage, inductance and switching frequency. Be sure to perform the margin check using the actual product.
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9/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Technical Note
(4) Selecting the output rectification diode Schottky barrier diode is recommended as the rectification diode to use at the DC/DC converter output stage. Select the diode paying attention to the max. inductor current and max. output voltage. Max. Inductor current IINMAX + IL < Rating current of diode Max. output voltage VOMAX < Rating voltage of diode Since each parameter has 30% to 40% of dispersion, be sure to design providing sufficient margins. (5) Design of the feedback resistor constant Refer to the following equation to set the feedback resistor. As the setting range, 10 k to 330 k is recommended. If the resistor is set to a 10 k or lower, it causes the reduction of power efficiency. If it is set to 330 k or larger, the offset voltage becomes larger by the input bias current 0.4 A (Typ.) in the internal error amplifier. Step-up Vo = R8 + R9 R9 1.245 [V] Vo R8 R9
2
Reference voltage 1.245 V
ERR
FB
Fig. 31Feedback Resistance Setting (6) Setting the soft start time Soft start is required to prevent the coil current at the time of startup from increasing and the overshoot of the output voltage at the starting time. Fig. 32 shows the relation between the capacitance and soft start time. Please refer to it to set the capacitance.
10
DELAY TIME[ms]
1
As the capacitance, 0.001 F to 0.1F is recommended. If the capacitance is set to 0.001 F, the overshooting may occur on the output voltage. If the capacitance is set to 0.1 F or larger, the excessive back current flow may occur in the internal parasitic elements when the power is turned OFF and it may damage IC. When the capacitor of 0.1 F or larger is used, be sure to insert a diode to Vcc in series, or a bypass diode between the SS pin and VCC.
Bypass diode
0.1
0.01 0.001
0.01 SS CAPACITANCE[uF]
0.1
Back current prevention diode
Fig.32 SS Pin Capacitance vs Delay Time
VCC
Output pin
Fig. 33 Bypass Diode Example When there is the startup relation (sequences) with other power supplies, be sure to use the high accuracy product (such as X5R). Soft start time may vary according to the input voltage, output voltage loads, coils and output capacity. Be sure to verify the operation using the actual product. (7) Setting the ENB pin When the ENB pin is set to Hi, the internal circuit becomes active and the DC/DC converter starts operating. When it is set to Low, the shut down is activated and all circuits will be turned OFF. (8) Setting the frequency by FCLK It is possible to change the switching frequency by setting the FCLK pin to Hi or Low. When it is set to Low, the product operates at 600 kHz (Typ.). When it is set to Hi, the product operates at 1,200 kHz (Typ.).
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10/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Technical Note
(9) Setting RC, CC of the phase compensation circuit In the current mode control, since the coil current is controlled, a pole (phase lag) made by the CR filter composed of the output capacitor and load resistor will be created in the low frequency range, and a zero (phase lead) by the output capacitor and ESR of capacitor will be created in the high frequency range. In this case, to cancel the pole of the power amplifier, it is easy to compensate by adding the zero point with CC and RC to the output from the error amplifier as shown in the illustration. Open loop gain
fp(Min) fp(Max) Gain dB lOUTMin lOUTMax fz(ESR) 0
A
fp = fz (ESR) =
1 2 Ro Co 1 2 ESR Co
[Hz] [Hz]
0 Phase deg -90
Pole at the power amplification stage When the output current reduces, the load resistance RO increases and the pole frequency lowers. fp(Min) = fz(Max) = 1 2 RoMax Co 1 2 RoMin Co [Hz] [Hz] (At light-load) (At heavy-load)
Error amplifier phase compensation
A Gain dB 0
Zero at the power amplification stage When the output capacitor is set larger, the pole frequency lowers but the zero frequency will not change. (This is because the capacitor ESR becomes 1/2 when the capacitor becomes 2 times.) fp (Amp.) = Fig. 34 Gain vs Phase
L Vo
Phase
0
deg-90
1 2 Rc Cc
[Hz]
VCC
Cin COMP Rc Cc
Vcc,PVcc SW
ESR
Ro
Co
GND,PGND
Fig. 35 Application Circuit Diagram It is possible to realize the stable feedback loop by canceling the pole fp (Min.), which is created by the output capacitor and load resistor, with CR zero compensation of the error amplifier as shown below. fz (Amp.) = fp (Min.) 1 2 Rc Cc = 1 2 Romax Co [Hz]
As the setting range for the resistor, 1 k to 10 k is recommended. When the resistor is set to 1 k or lower, the effect by phase compensation becomes low and it may cause the oscillation of output voltage. When it is set to 10 k or larger, the COMP pin becomes Hi-Z and the switching noise becomes easy to superpose. Therefore the stable switching pulse cannot be generated and the irregular ripple voltage may be generated on the output voltage. As the setting range for the capacitance, 3,300 pF to 10,000 pF is recommended. When the capacitance is set to 3,300 pF or lower, the irregular ripple voltage may be generated on the output voltage due to the effect of switching noise. When it is set to 10,000 pF or larger, the response becomes worse and the output voltage fluctuation becomes large. Accordingly it may require the output capacitor which is larger than the necessary value.
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11/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Technical Note
(10) Using the buffer amp and VCOM The 4-channel buffer amp and 1-channel VCOM output are used to generate the gamma compensation voltage that is input to the source driver. The VS pin serves as the power supply for the buffer amp and VCOM. VS
VCOMIN VIN1 VIN2 VIN3 VIN4
VCOM voltage output V1 V2 V3 V4 For gamma correction Gamma correction voltage output
Fig. 36 Example Buffer Amp Circuit Use caution as the gamma correction buffer amp and VCOM have different output current capacities. A range from I/O power supply to ground potentials can be set for the built-in buffer amplifier. If output voltage noise becomes problematic, insert a 0.1 F capacitor in the output circuit. A capacitance value of 0 pF to 1 F is recommended for this capacitor. Large capacitance values of 1 F or larger may cause back current to flow through internal parasitic diodes in the event of a supply voltage ground fault, causing damage to internal IC elements. For applications where such modes are anticipated, implement a bypass diode or other preventive measure.
Wait for trigger
Vs V1 V2 V3 V4
Fig. 37 Gamma Correction Voltage Startup Waveform
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12/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Technical Note
Application Examples * Although ROHM is sure that the application examples are recommendable ones, further check the characteristics of components that require high precision before using them.When a circuit is used modifying the externally connected circuit constant, be sure to decide allowing sufficient margins considering the dispersion of values by external parts as well as our IC including not only the static but also the transient characteristic. For the patent, we have not acquired the sufficient confirmation. Please acknowledge the status. (1) When the charge pump is removed from the DC/DC converter to make it 3-channel output mode: It is possible to create the charge pump by using the switching operation of DC/DC converter. When the application shown in the following diagram is used, 1-channel DC/DC converter output, 1-channel positive side charge pump and 1-channel negative side charge pump can be output as a total of 3 channels. 0.1uF
0.1uF 10uH 10uF
VOUT DAN217U RB161M-20
1 SW
CURRENT SENSE
20 PGND 19 GND DRV SET
1uF
1uF 2SD2657k
VCC 2.5V
10uF
2 VCC 3 ENB 4 FCLK 5 VS UVLO TSD SLOPE
+
OSC
LOGIC
RESET SDWN OCP
18 ERR + 1.245V FB
0.1uF UDZ Series
VGH
PWM +SOFT START
17 COMP 16 SS
BUFFER SUPPLY
DAN217U
1uF
6 COMIN 7 IN1 8 IN2 9 IN3 10 IN4 TOP VIEW
15 VCOM 14 OUT1 13 OUT2 12 OUT3 11 OUT4
VCOM 1uF V1 V2 V3 V4 UDZ Series 1uF 2SB1695k VGL
Fig. 38 3 ch Application Circuit Diagram Example (2) When the output voltage is set to 0 V: Since the switch does not exist between the input and output in the application using the step-up type DC/DC converter, the output voltage is generated even if the IC is turned off. When it is intended to keep the output voltage 0 V until IC operates, insert the switch as shown in the following circuit diagram.
10uH RB161M-20 10uF
Vo
1 SW
CURRENT SENSE
20 PGND 19 GND DRV SET
VCC 2.5V
10uF
2 VCC 3 ENB 4 FCLK 5 VS UVLO TSD SLOPE
+
OSC
LOGIC
RESET SDW N OCP
18 ERR + 1.245V FB
PW M +SOFT START
17 COMP 16 SS
BUFFER SUPPLY
6 COMIN 7 IN1 8 IN2 9 IN3 10 IN4 TOP VIEW
15 VCOM 14 OUT1 13 OUT2 12 OUT3 11 OUT4
VCOM V1 V2 V3 V4
Fig. 39 Switch Application Circuit Diagram Example
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13/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
I/O Equivalent Circuit Diagrams 1.SW
Technical Note
11.OUT4 12.OUT3 13.OUT2 14.OUT1 15.VCOM VS
3.ENB Vcc
4.FCLK
16.SS Vcc
200k
6.COMIN 7.IN1 8.IN2 9.IN3 VS
10.IN4
17.COMP
18.FB
Vcc
Fig.40 I/O Equivalent Circuit Diagrams
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14/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Technical Note
Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on an application board. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in Fig. 41, a parasitic diode or a transistor operates by inversing the pin voltage and GND voltage. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as the application of voltages lower than the GND (P substrate) voltage to Resistor input and output pins. Transistor (NPN) (Pin B)

(Pin A) B (Pin B)

C

GND
E
B
C E GND Parasitic elements
P N N P
P
N P N Parasitic element N P N P substrate Parasitic elements GND GND P P N (Pin A)
GND
Parasitic element
Fig.41 Example of a Simple Monolithic IC Architecture
9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC destruction that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) Thermal shutdown circuit (TSD) This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's temperature Tj will trigger the temperature protection circuit to turn off all output power elements. The circuit automatically resets once the chip's temperature Tj drops. Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC.
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15/17

2009.07 - Rev.B
BD8151EFV, BD8157EFV
Power Dissipation Reduction DISSIPATION :
Technical Note
2000 1500 1000 1000 500 0 25 50
On 70x70x1.6mm Board
POWRE
BD8151EF BD8157EF
75 85
100
125
150
AMBIENT MPERATURE :Ta[] Fig.42 Power Dissipation Reduction
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
16/17
2009.07 - Rev.B
BD8151EFV, BD8157EFV
Ordering part number
Technical Note
B
D
8
Part No. 8151 8157
1
5
1
E
F
V
-
E
2
Part No.
Package EFV : HTSSOP-B20
Packaging and forming specification E2: Embossed tape and reel
HTSSOP-B20
6.50.1 (MAX 6.85 include BURR) (4.0)
20 11

Tape Quantity
0.50.15 1.00.2
Embossed carrier tape (with dry pack) 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.40.2
4.40.1
Direction of feed
(2.4)
( reel on the left hand and you pull out the tape on the right hand
)
1
10
0.325
1.0MAX
+0.05 0.17 -0.03 S
0.850.05
0.080.05
0.65 +0.05 0.24 -0.04
0.08 S
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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17/17
2009.07 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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